Dolphin Integration rolls IPs to cut 65-nm silicon area – EETimes.com

- Architectural Metal

Dolphin Integration rolls IPs to cut 65-nm silicon area EETimes.com … challenge at the architectural level. The panoply includes Single Port and Dual Port RAMs, metal programmable ROMs, Register Files and standard cells

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Architectural Metal – Dolphin Integration rolls IPs to cut 65-nm silicon area – EETimes.com

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